Working notes. Some describe a design I have not built yet, others an experiment in progress. Where something is finished, the artifact or result is linked.
Accelerator architecture
- Zero to NPU: a nine-phase learning roadmap for an int8 accelerator on a Zynq FPGA.
- Inside a systolic array: an interactive matrix-engine visualization and its verification approach.
- Run the systolic array animation ↗
Local AI infrastructure
- Two Pools: a fourteen-module roadmap for running a 30B mixture-of-experts coding model on a 16 GB GPU, built around the bandwidth gap between VRAM and system memory.
Digital design
- RISC CPU: Verilog datapath and instruction-level simulation artifacts.
- FPGA exercises: digital logic exercises targeting the Real Digital Blackboard.
- RV32I design plan: a planning document for a RISC-V processor. The public repository does not yet include an RTL implementation.