Weight-stationary systolic array

The matrix engine at the heart of an NPU. Weights sit still; activations stream left→right, partial sums fall top→bottom, and every cell does one int8×int8 multiply-accumulate per clock.

Cycle
0
MACs this cycle
0
Utilization
0%
Total MACs
0
vs. 1 MAC/cycle
—
weight (stationary) activation → partial sum ↓ output int32

What to watch. Activations enter each row one cycle later than the row above — that staircase skew is what makes a value meet the right partial sum. A partial sum enters the top of a column at zero and grows by psum += act × weight in every cell it passes, dropping out of the bottom as a finished int32 dot product.

Why NPUs are built this way. Each activation is fetched from memory once and then reused across the whole row; each weight is loaded once and reused for every token. After the pipeline fills, all R×C cells compute every cycle — so the array does R×C MACs per clock while performing only O(R+C) memory accesses. That data-reuse ratio, not the multiplier count, is the actual reason systolic arrays win.