Reference Material

Part of Zero to NPU.

Pull these as you need them, not up front

Reading all of this before you start is a procrastination strategy. Each entry is tagged with the phase where it becomes relevant.


Core

Theory

TopicSourceNeeded by
Quantization mathJacob et al., Quantization and Training of Neural Networks for Efficient Integer-Arithmetic-Only Inference (the gemmlowp paper)phase-2-numerics
Systolic arraysJouppi et al., In-Datacenter Performance Analysis of a TPU (§ on the MXU)phase-3-mac-engine
Online softmaxMilakov & Gimelshein, Online normalizer calculation for softmaxphase-5-vector-unit

Prior art — read, don’t copy

ProjectWhy it’s useful
Leonui/tiny-npu16×16 int8 array, real GPT-2/LLaMA weights, cycle-accurate golden models. Closest architectural match. Note: FPGA synthesis is still a roadmap item there — it’s a simulation project.
Buck008/Transformer-Accelerator-Based-on-FPGAParameterized systolic array that actually runs on Zynq hardware today. Sized for a Z1/Z2 — you’ll need to shrink it.
taoFPGA/acceleratorFused matmul → softmax → GELU in int8 streaming RTL on Zynq-7000.

Calibration

SourceWhat it tells you
LlamaF (arXiv 2409.11424)TinyLlama-1.1B at 1.5 tok/s on a ZCU102 — a board vastly larger than yours. Useful for calibrating what’s genuinely hard, and for understanding why your Tier 2 capstone is slow.

On the Zynq-7020 data point

One published 16×16 int8 array on a 7020 mapped only 64 of 256 multipliers to DSPs — the other 192 became fabric multipliers, consuming most of a 59% LUT occupancy.

The 7020 has 220 DSPs. You have 60. This is the clearest available evidence that 16×16 is not reachable on your part, and why 8×4 is the right call.